A method and equipment of this kind are for instance described in U.S. Pat. No. 4,821,292, disclosing a receiver unit comprising a data recovery circuit comprised of a comparator, an RC network, a modem/dotting pattern detector and a microprocessor. The comparator circuit compares the voltage level of an input signal with a threshold DC reference voltage or slice level, and determines whether a logic “1” or a logic “0” is represented by the analog signal. The resulting bitstream is provided to the modem/dotting pattern detector which converts the serial data signal to a parallel signal. The incoming analog signal which is evaluated by the comparator, represents a data message comprised of a preamble or dotting pattern and a message part. During transmission of the dotting pattern, the time constant of the RC network is decreased in order to be able to adapt the DC voltage or slice level quickly during the preamble part of the data signal.
In present wireless telecommunications systems, such as the well-known mobile GSM (Global System for Mobile communication) and cordless DECT (Digital Enhanced Cordless Telecommunication) radio communications systems, information to be exchanged is digitally processed. For transmission purposes, the digital data are suitably modulated on an RF carrier and transmitted as an analog data signal.
In the radio receiver part of radio equipment of such radio communications systems, after demodulation, for processing purposes, the received analog data signal is converted into a digital data signal again by means of a data recovery circuit, also called a data slicer.
International patent application WO 93/26110 discloses a data recovery circuit wherein the decision as to whether the currents value of the analog data input signal represents a binary null or a binary one is performed by comparing whether the analog data input signal is above or below a predetermined threshold or slice level. The slice level is derived from the analog data input signal by means of an integrator circuit comprising a resistor and capacitor connected as a Low Pass (LP) filter.
The slice level must be able to vary in order to adjust to a particular received data input signal. To this end, by means of switches, resistors of different values can be selected for increasing or decreasing the integration time constant of the integrator circuit.
Savings in the number of components, the space which components take on a Printed Circuit Board (PCB), and manufacturing costs are important design criteria in modern wireless telecommunications transceiver equipment.
Analog data slicers of the type disclosed above require a lot of discrete electronic components. Further, for changing the integration time constant, hardware has to be changed, i.e. resistors and/or capacitors.
It has been observed that in communications systems operating in accordance with a Time Division Multiple Access (TDMA) transmission scheme, wherein data are exchanged in frames and each frame comprises a number of bursts or time slots, after the detection of the so-called synchronization or sync word, a DC offset occurs in the threshold or slice level. The sync word is a particular string of bit values (ones and zeroes) which have to be identified by the receiver equipment in order to process the received data correctly.
The offset in the slice level is caused by the specific bit pattern of the sync word, i.e. an unequal number of ones and zeroes, which cannot be compensated for by the analog data slicer, and which degrades the receiver sensitivity and performance.
Other sources of DC offset in a receiver are, among others, frequency deviations in reference oscillators, transmitter frequency differences, demodulator offset, and interferer signals received by the receiver.
In cellular GSM or DECT radio communications systems, for example, radio base stations or radio access units provide service to a plurality of remote radio communication units in a particular geographical area, also called a cell. At a particular radio base station or radio access unit, for each communications link, that is an RF carrier/time slot combination, the DC slice level offset may vary, among others, dependent on the distance between the radio base station and a radio communication unit, the transmission power of the radio communication unit, whether or not the radio communication unit operates in or outside a building, etcetera.
In order to adapt the data slicer to a particular DC offset during reception, the above disclosed known analog data slicer circuit provides a hold modus for holding the slice level from the previously received time slot for use with the next time slot.
However, in a GSM or DECT radio communications system, the previous time slot of a frame generally belongs to a different communications link with different transmission properties. Accordingly, information as to the slice level experienced during a previous time slot will not necessarily be valid for the next time slot.
Receiver performance would be greatly improved if, for each communications link individually, a particular slice level could be set at the start of each time slot.